This invention relates to programmable logic device integrated circuits, and more particularly, to latch circuits for programmable logic devices.
Integrated circuits typically contain combinational logic and sequential logic. Combinational logic does not include storage elements. The output of a given combinational logic circuit is therefore determined solely by its present inputs. Sequential logic circuits contain storage elements that reflect their past behavior. As a result, the output of a sequential circuit is determined by both its present inputs and by the data stored in its storage elements.
Commonly-used sequential circuit storage elements include level-sensitive latches and flip-flops.
In a level-sensitive latch, the latch output is controlled by the level of a clock (enable) input. When the clock is high, the latch output tracks the value of the input. When the clock transitions from high to low, the output state of the latch is frozen at whatever value was present just prior to the transition. So long as the clock is low, the output of the latch will be maintained in its frozen state.
Flip-flops are edge-triggered devices that change state on the rising or falling edge of an enable signal such as a clock. In a rising-edge-triggered flip-flop, the flip-flop samples its input state only at the rising edge of the clock. This sampled value is then maintained until the next rising edge of the clock.
Flip-flop-based logic circuits are often preferred over latch-based circuits, because the regularity imposed by the edge-triggered properties of flip-flops makes circuit timing behavior relatively straightforward to model.
However, latch-based circuits can offer performance improvements over flip-flop-based circuits. In a flip-flop-based logic circuit, the clock frequency must generally be slowed down sufficiently to accommodate the delay associated with the circuit's slowest combinational logic paths. Even if circuitry in a fast logic path produces a valid signal in less time than a slow logic path, that signal is not used until the edge of the next clock pulse. While this regularity is beneficial for ease of circuit design, it tends to limit performance in certain situations.
In latch-based circuits, the time allocated for each combinational logic stage need not be identical. In certain paths, where the delay is small, the ability of the output of a latch to immediately track its input without waiting for the next clock edge can be exploited to gain extra time. The extra time gathered from such logic paths can be shared with other paths. This approach allows slow paths to borrow time from faster paths, so the clock speed for the entire circuit need not be slowed to accommodate worst-case delays.
Because of these attributes, latch-based architectures are sometimes used in high-performance integrated circuits where performance is more important than ease of design.
Programmable logic device integrated circuits are a type of integrated circuit in which a user can configure logic to perform a desired custom logic function. Programmable logic circuits generally use flip-flop-based logic architectures.
It would be desirable to be able to use latch-based circuit arrangements in programmable logic device integrated circuits.